Why Data Movement Becomes the Bottleneck

A modern AI accelerator is not valuable in isolation. Training and inference increasingly depend on distributed computation across many processors, and each processor must exchange data with memory and neighboring processors at extraordinary rates. The faster the arithmetic units become, the more damaging idle time becomes. A trillion operations per second is irrelevant if the processor spends too much of its time waiting for data.

Communication has two separate costs. The first is latency: how long the information takes to arrive. The second is energy: how much power the system consumes to move each bit. AI systems make both important. Large synchronous training jobs can stall when one part of the cluster falls behind. At the same time, network and I/O power competes directly with the accelerators for the facility’s electrical and cooling budget.

This is why network architecture is becoming part of compute architecture. NVIDIA describes networking as the fabric that allows AI data centers to operate as distributed engines rather than collections of independent servers. Broadcom frames CPO around scale-up and scale-out AI fabrics. Intel’s optical I/O research explicitly targets CPU, GPU, IPU and other system-on-chip connectivity. The industry is no longer treating optical networking as something that begins at the server’s edge. It is asking how far inside the system photons should travel.

What Limits Electrical I/O

Copper is not failing because electrons suddenly became slow. The limitation is signal integrity at very high frequencies. Fast electrical signaling suffers attenuation, reflections, crosstalk and distortion. Engineers compensate using sophisticated serializer/deserializer circuits, equalization, forward-error correction, retimers and digital signal processing. Those techniques are remarkable engineering achievements, but they consume power and silicon area.

Broadcom explains the CPO transition in exactly these terms. Today’s pluggable optical modules receive high-speed electrical signals after those signals travel from the switch ASIC across the package and circuit board. As electrical lane rates increase toward 212 gigabits per second and beyond, losses rise and the module’s DSP has to compensate. Moving the photonic engine directly beside the ASIC shortens the difficult electrical path dramatically.

Electrical links remain attractive at very short distances because the transceiver overhead of optics is not free. Lasers consume power. Modulators require drivers. Photodetectors need receivers. Fibers have to be attached precisely. Optical engines must be manufactured and tested. The architectural question is therefore not “Why not replace every wire with fiber?” It is “At what bandwidth and distance does the electrical path become more expensive than conversion to optics?”

What Silicon Photonics Actually Is

Silicon photonics uses semiconductor fabrication to build circuits that guide and manipulate light. A silicon-photonics integrated circuit can contain waveguides that route photons, modulators that encode electrical information onto light, photodetectors that convert light back into electrical signals, couplers that connect chip-scale waveguides to fiber and increasingly complex optical switching structures.

The attraction is manufacturing. Conventional optical systems historically relied on many discrete components assembled with precision. Silicon photonics moves more of those functions into lithographically fabricated structures compatible with wafer-scale semiconductor processes. A 2025 Nature Reviews Electrical Engineering review describes the field as reaching integration maturity across lasers, optical amplifiers, modulators, detectors, waveguides and chip-to-fiber interfaces while increasingly relying on 3D and heterogeneous integration with advanced electronics.

Silicon itself is not an ideal light emitter, so laser architecture remains one of the most important integration choices. Intel has developed hybrid laser-on-wafer integration. Other architectures place lasers externally and route optical power into co-packaged engines. Materials such as indium phosphide, silicon nitride, thin-film lithium niobate and others can be integrated where silicon alone is not optimal. “Silicon photonics” is therefore often a heterogeneous technology stack rather than a pure-silicon device.

The Pluggable Optics Era

Today’s data centers already use enormous quantities of optical technology. High-speed pluggable transceivers sit in the front panels of switches and network interfaces. They convert electrical signals from the system into light, send that light through fiber and convert incoming optical signals back into electrical data. Their great advantage is modularity: if an optical module fails, a technician can replace it without replacing the switch ASIC.

Pluggables also support multi-vendor ecosystems. Standard form factors, management interfaces and optical specifications allow network operators to buy compatible modules from different suppliers. That serviceability and market flexibility has enormous operational value. It explains why CPO has faced a higher adoption threshold than a laboratory power comparison might suggest.

The weakness is the electrical path between ASIC and module. As switch radix and lane rate rise, traces from a very large switching ASIC to dozens of front-panel modules become increasingly difficult. Power that is spent recovering the signal after that electrical journey produces no application-level computation. CPO attempts to eliminate much of that path by moving the electro-optical conversion onto the package substrate beside the ASIC.

Why Co-Packaged Optics Moves Light Closer

Co-packaged optics combines high-performance electronics and optical engines in one package or tightly integrated substrate. Instead of transmitting a fragile high-speed electrical signal across a large section of circuit board before converting it to light, the system performs optical conversion close to the switch or compute ASIC. Fiber then carries the signal away.

Broadcom says its CPO architecture produces greater than 3.5-times optical power savings and roughly forty percent lower optics cost per bit compared with conventional approaches in its own product analysis. NVIDIA says its CPO switching architecture delivers five-times better network power efficiency than traditional pluggable transceiver-based networks. TSMC says COUPE integration provides twice the power efficiency and ten-times lower latency than a pluggable version on the circuit board. These are vendor-specific comparisons with different assumptions, not universal constants, but the direction is consistent: shorter electrical reach improves the system power budget.

The cost is integration complexity. The switch ASIC is one of the most expensive and thermally demanding components in the system. Placing optical engines beside it means the optics must survive package manufacturing, heat, mechanical stress and field operation. Fiber attachment becomes part of the system assembly. Optical-engine yield can affect package economics. A failure can become harder to service. The architecture gains electrical efficiency by taking on packaging risk.

NVIDIA’s Production Push

NVIDIA’s importance is not that it invented silicon photonics. It is that the dominant supplier of AI accelerators is integrating photonics directly into its networking roadmap. NVIDIA’s Spectrum-X Ethernet Photonics and Quantum-X InfiniBand Photonics platforms place silicon-photonics engines on the switching package and are designed for the enormous network scale of future AI infrastructure.

NVIDIA lists Spectrum-X Ethernet Photonics at up to 409.6 terabits per second of switching bandwidth and says product availability begins in the second half of 2026. The company also says Spectrum-X Ethernet Photonics has moved into full production through collaboration with TSMC and a broader optical supply chain. First adopters listed by NVIDIA include major cloud and AI infrastructure operators. These are strong deployment signals, but the company’s efficiency and application-runtime comparisons remain vendor claims.

The strategic point is more important than any one multiplier. NVIDIA has historically built scale-up and scale-out fabrics as part of the GPU platform. Putting CPO inside that stack means optics is becoming part of the accelerator-system roadmap rather than a third-party networking afterthought.

Broadcom and Production CPO

Broadcom represents a different but equally important route. The company builds switching silicon, SerDes, DSPs and optical technology and says it is shipping production CPO systems today. Its BCM78919 combines a 102.4-terabit-per-second switching architecture with 200-gigabit-per-second SerDes and co-packaged silicon photonics. The product is listed in limited release rather than broad commodity availability.

At OFC 2026, Broadcom described a transition toward what it calls the 200-terabit AI era and reported sixty-five-percent power savings for some of its CPO comparisons against retimed pluggable optics. The company simultaneously acknowledged that pluggable optics remains the immediate solution for much of the market while CPO matures through packaging, process and reliability improvements.

That nuance matters. CPO does not win merely because the physics is attractive. It has to beat a massive installed ecosystem of pluggable modules whose manufacturing, field replacement and multi-vendor operations are extremely mature.

TSMC Turns Photonics Into Packaging Infrastructure

TSMC’s role shows why the photonics story is inseparable from advanced packaging. The foundry’s COUPE technology uses 3D chip stacking to integrate electrical and photonic dies. TSMC’s current roadmap places true co-packaged optical integration into production in 2026, with the photonic engine integrated directly inside the package.

That development connects photonics to the same advanced-packaging ecosystem that already links AI compute dies and HBM. In other words, the optical engine is becoming another chiplet-class component in a heterogeneous package. The strategic manufacturing question shifts from “Can a photonic device work?” to “Can electronics, memory and photonics be assembled, tested and yielded together at scale?”

TSMC says its 2026 COUPE implementation offers twice the power efficiency and ten-times lower latency than a corresponding pluggable-on-board architecture. Those figures are foundry claims tied to TSMC’s implementation, but they demonstrate why hyperscale customers are pushing optical conversion into advanced packaging rather than treating it solely as a network-module problem.

Intel’s Optical Compute I/O

Intel provides one of the clearest examples of optics moving from switch networking toward compute I/O. Its Optical Compute Interconnect chiplet integrates a silicon-photonic circuit with on-chip lasers and optical amplifiers plus a CMOS electrical die. Intel’s first-generation design supports four terabits per second bidirectionally and is intended to be co-packaged with CPUs, GPUs, IPUs or other system-on-chip devices.

Intel demonstrated the chiplet with a CPU and a live optical link, but its own documentation still labels the original implementation a prototype and says it is working with selected customers toward co-packaged optical I/O. That maturity language is important. The silicon-photonics platform beneath the chiplet is commercially mature—Intel says it has shipped more than eight million PICs and more than thirty-two million integrated on-chip lasers in pluggable applications—but optical I/O directly beside compute is a newer deployment stage.

If this architecture scales, the boundary between “network” and “processor I/O” becomes less meaningful. A GPU package could communicate through fiber over distances that are awkward for electrical links without routing through the same hierarchy of board-level electrical interfaces used today. That opens possibilities for larger disaggregated compute domains and memory pools, but it also requires entirely new packaging and fabric architectures.

Lightmatter and the Optical-Interposer Thesis

Lightmatter is pursuing one of the more aggressive versions of the optical-I/O architecture. Its Passage platform uses photonic interposers and optical engines designed to connect processors with extremely high bandwidth density. In March 2026 the company announced a Passage L20 optical engine delivering 6.4 terabits per second in each direction for near-package and on-board optics applications, with sampling expected later in 2026.

Lightmatter separately reported a 1.6-terabit-per-second-per-fiber demonstration using dense wavelength-division multiplexing and announced detachable fiber-attachment technology intended to improve serviceability in high-volume CPO packaging. These are vendor demonstrations and roadmap claims rather than proof of broad hyperscale deployment, but they attack exactly the problems holding CPO back: bandwidth density, fiber count, integration and field service.

The company’s broader “edgeless I/O” thesis addresses a geometric limit. Conventional electrical I/O tends to escape a chip around its perimeter. Compute area can grow faster than available edge length. A vertically integrated optical interposer can potentially distribute I/O across more of the package area rather than treating the die edge as the only route out. If manufacturable, that changes the scaling law for accelerator packages.

The Laser Problem

Silicon can guide and manipulate light effectively, but generating light efficiently is more difficult. That makes the laser source a central design choice. Intel integrates lasers on its photonics platform through heterogeneous laser-on-wafer techniques. Other CPO architectures prefer external lasers because lasers operate more reliably away from the hottest parts of the switch package and can be replaced independently if they fail.

OIF’s External Laser Small Form-Factor Pluggable specification exists for exactly this reason. It defines a front-panel removable laser source capable of feeding one or more co-packaged optical engines. The laser sits in a cooler, accessible part of the chassis while optical fibers route the light to the package. OIF continued demonstrating external-laser interoperability at OFC 2026 as part of the industry’s CPO commercialization work.

Lightmatter is experimenting with another physical arrangement through its Guide DR laser NIC, which moves dense laser infrastructure into a liquid-cooled in-chassis card rather than consuming scarce front-panel space. The existence of these different architectures demonstrates that CPO is not one solved product format. The optical engine may be mature enough to justify deployment while the industry still debates where the light source should live.

Serviceability and Reliability

A photonic link that works in a laboratory can be useless operationally if a failed component forces replacement of an expensive switch package. This is the strongest practical argument for pluggable optics: replace the transceiver, not the switch. CPO has to recreate that operational flexibility through different mechanisms.

Detachable fiber arrays, external lasers, modular optical engines, redundancy and package-level diagnostics are all attempts to solve the service problem. Lightmatter’s 2026 vClick announcement is explicitly about detachable fiber attachment for CPO manufacturing and field replacement. OIF’s external-laser standards similarly make the laser source hot-swappable rather than permanently binding every optical component to the ASIC package.

Reliability is also thermal. Switch ASICs and accelerators operate at high power density. Photonic resonators can be temperature sensitive. Lasers dislike heat. Fiber couplers must survive mechanical movement and repeated thermal cycling. A CPO system that saves link power but creates unacceptable repair rates does not improve data-center economics. This is why vendor claims about efficiency need to be evaluated alongside field serviceability and fleet uptime.

Why One Fiber Can Carry Many Channels

One reason optics scales so effectively is wavelength-division multiplexing. Different colors—or wavelengths—of light can carry independent data channels through the same fiber. Instead of assigning one physical conductor to each high-speed lane, an optical system can combine many wavelengths, transmit them together and separate them at the destination.

Dense wavelength-division multiplexing increases bandwidth per fiber and reduces the physical fiber count required for a given data rate. Lightmatter’s 2026 1.6-terabit-per-second-per-fiber demonstration used sixteen wavelengths. Intel’s optical I/O roadmap similarly uses wavelength multiplexing to increase chiplet bandwidth. Modern pluggable transceivers already use related techniques extensively.

The price is complexity in lasers, wavelength control, thermal tuning, modulators and optical filters. More wavelengths create more total capacity, but every channel has to remain stable enough for the receiver to distinguish it under real operating conditions. Photonics trades some of copper’s signal-integrity problems for optical-control problems of its own.

Scale-Up Versus Scale-Out Optics

AI networking contains several distance domains. Scale-up fabrics connect accelerators that need to cooperate extremely tightly, often inside a rack or rack-scale system. Scale-out fabrics connect many such systems across a larger cluster. Scale-across fabrics increasingly connect entire data centers or campuses. Optics reached the longest domains first because electrical links could not serve them. The frontier is now scale-up.

That migration matters because scale-up links demand exceptionally low latency and very high bandwidth. Electrical fabrics such as NVLink remain powerful because they minimize protocol and conversion overhead at short range. Optical I/O has to match enough of that behavior while offering longer reach and higher bandwidth density. This is why the most advanced photonics companies increasingly talk about “scale-up optics” rather than ordinary data-center networking.

The winning architecture may be hybrid. Copper may remain dominant within the tightest package or rack domain where distance is short and serviceability is valuable. Optics may begin at the rack boundary for one generation, then move closer as lane rates rise. There is no requirement that the transition happen everywhere at once.

The Memory and Chiplet Horizon

The next frontier is not only GPU-to-GPU communication. AI systems increasingly depend on HBM, pooled memory and heterogeneous chiplets. Advanced packaging already places compute dies and memory stacks close together because electrical bandwidth is highest at short distance. Optical I/O raises the possibility that some resources could move farther away without paying the same electrical reach penalty.

Intel explicitly describes optical I/O as potentially supporting coherent memory expansion and resource disaggregation. In principle, processors could access pools of memory, accelerators or other resources across fiber while preserving more bandwidth and energy efficiency than board-scale copper would allow. That could change how servers are physically assembled.

But optical reach does not make remote memory local. Propagation delay, protocol overhead, serialization and switching still exist. Photonics can reduce the energy and reach penalty of communication; it cannot erase latency imposed by distance. The strongest architectures will use light to expand the useful radius of high-bandwidth connectivity without pretending every resource is equally close.

Optical Interconnect Versus Photonic Computing

The phrase “computers use light” can mean two very different things. Optical interconnect uses photons to move digital information between electronic computing elements. Photonic computing attempts to perform part of the computation itself in optical hardware. The first is entering commercial infrastructure. The second is advancing rapidly but remains more specialized.

A 2026 Light: Science & Applications paper demonstrated a programmable silicon-photonic system capable of matrix multiplication, signal processing and switching. A separate 2026 Nature Communications paper demonstrated an integrated photonic tensor processor for neural-network inference in a rack-scale system. These are significant research results because analog photonics can perform some linear algebra with extremely low latency and potentially high energy efficiency.

But photonic computation has limitations that do not disappear in impressive throughput figures. Memory remains largely electronic. Nonlinear functions are difficult. Precision can be lower than digital arithmetic. Converting information between electrical and optical domains has cost. Training and general-purpose control still depend heavily on electronic systems. Photonic accelerators are therefore more likely to complement CPUs and GPUs in specialized workloads than to replace digital electronics wholesale in the near term.

The maturity distinction is crucial: optics is becoming necessary for communication before it becomes general-purpose computation. That is why this article treats photonic neural processors as a separate research lane rather than evidence that conventional digital logic is about to disappear.

Standards Become Infrastructure

Optics becomes economically powerful when it becomes interoperable. OIF’s Common Electrical I/O work now spans 224-gigabit-per-second interfaces and a 448G framework. At OFC 2026, OIF demonstrated multi-vendor 448G and 224G electrical/optical interoperability alongside retimed, half-retimed and linear optics. That work matters because the electrical interface between switch silicon and optical engines must itself evolve as lane rates rise.

OIF’s Common Management Interface Specification provides another unglamorous but essential layer. Operators need consistent ways to configure modules, retrieve diagnostics, update firmware and manage external laser sources. A CPO ecosystem in which each vendor requires proprietary management would be difficult to operate at hyperscale.

Standards also protect against vertical lock-in. A fully integrated vendor can optimize ASIC, photonics, fiber and management as one stack, but hyperscalers often want multiple sources for critical components. The long-term success of CPO may depend on finding the right balance between tight co-design and modular interoperability.

What Is Actually Mature?

The photonics landscape spans mature commodity technology, first production deployments and frontier research simultaneously. Treating all of it as one “optical computing revolution” obscures the engineering reality. Optical transceivers are ordinary infrastructure. Silicon-photonics transceivers have shipped at volume. CPO is entering production and limited release in major switching platforms. Optical I/O beside CPUs and GPUs is advancing from prototype toward customer evaluation. Photonic neural computation remains a specialized research and early-product domain.

The SURVXCOM Optical Scaling Test

An optical technology should not be judged by the fastest laboratory lane or the most dramatic aggregate bandwidth number alone. The relevant question is whether the complete interconnect system improves useful computing after packaging, power, reliability and operations are counted. SURVXCOM therefore evaluates optical scaling across twelve layers.

What to Watch Next

NVIDIA’s 2026 production ramp. Watch actual Spectrum-X and Quantum-X Photonics shipments, customer deployment scale, failure rates and operational experience rather than relying only on stated power-efficiency multipliers.

Broadcom production CPO. Broadcom says production systems are already shipping. Watch whether CPO adoption expands from limited hyperscale deployments into broader switch platforms and whether its service model proves competitive with pluggables.

TSMC COUPE. The key milestone is volume packaging, not another photonic-device demonstration. Watch customer tape-outs, yield, advanced-packaging integration and whether COUPE becomes a standard photonic engine within CoWoS-class AI packages.

Intel OCI customer evaluation. Intel’s underlying silicon-photonics manufacturing is mature, but compute-package optical I/O remains earlier. Watch movement from prototype to customer-qualified chiplet and eventually production SoC integration.

Scale-up optics. The largest architectural prize is moving fiber inside the accelerator domain. Watch whether optical I/O begins displacing copper in rack-scale GPU/TPU fabrics rather than only switch-to-switch links.

External laser standardization. OIF ELSFP and competing laser architectures will determine how operators balance thermal reliability, faceplate space and serviceability.

448G electrical interfaces. Faster optics still begins and ends in electronics. Watch OIF CEI-448G as the electrical edge feeding next-generation optical engines.

Pluggable survival. Linear and retimed pluggables continue improving. Watch whether better pluggable architectures postpone CPO for some applications by reducing DSP power without surrendering field replaceability.

Detachable fiber attachment. High-density fiber connections have to become manufacturable and serviceable. Watch whether detachable array technologies move beyond vendor demonstrations into standardized high-volume packaging.

Photonic compute reality. Continue separating optical I/O from optical neural accelerators. Photonic tensor processors may become valuable specialized accelerators, but that is a different maturity path from CPO networking.

When Computers Use Light

The history of computing is often told through logic devices: vacuum tubes, transistors, integrated circuits, microprocessors and GPUs. But every increase in computational density eventually creates a communication problem. A processor needs memory. One chip needs another. One server needs a switch. One rack needs the rest of the cluster. At sufficient scale, the computer is defined as much by the fabric connecting its parts as by the arithmetic inside each part.

That is why silicon photonics belongs beside semiconductors, power and advanced packaging in the Critical Technology Stack. The AI infrastructure race cannot be understood by counting GPUs alone. A million accelerators are not one computer unless data can move among them with acceptable latency, power, reliability and cost.

Light changes the scaling equation because distance affects optical links differently from high-speed copper. Once information is converted into photons, the same physical fiber can carry enormous aggregate bandwidth over distances that become progressively harder for electrical traces. Wavelength multiplexing lets one fiber carry many independent channels. The physical properties that made fiber indispensable for telecommunications are now becoming relevant inside the computer itself.

The transition will be uneven. Electrical I/O will remain dominant wherever its simplicity and short-reach efficiency win. Pluggable optics will remain attractive where serviceability matters. Co-packaged optics will gain ground where switch bandwidth and electrical loss become intolerable. Optical I/O may move beside GPUs and CPUs when package-edge bandwidth becomes the next wall. Photonic computing may eventually accelerate specialized mathematical operations, but it should not be confused with the much nearer transition in interconnect.

The decisive engineering work will look less glamorous than the phrase “computing with light.” Lasers have to survive. Fibers have to attach. Packages have to yield. Photonic circuits have to tolerate heat. Standard interfaces have to exist. Technicians need to replace failed components. Operators need telemetry. The optical supply chain has to scale alongside advanced packaging and semiconductor manufacturing.

If those pieces come together, the architecture of the data center changes quietly. The board trace becomes fiber. The front-panel module moves into the package. The network edge moves toward the processor. Separate servers become larger optical compute domains. Memory and accelerators can be placed where power, cooling and packaging economics make sense rather than only where electrical reach permits.

This is what it means for computers to begin using light. It is not a replacement for silicon logic. It is the recognition that silicon logic has become powerful enough that the wires connecting it are now one of the constraints.

The optical era begins when computation can no longer scale economically unless the data leaves the chip as light. The decisive transition will be measured not by a dramatic optical-computer announcement, but by how routinely photons replace high-cost electrical distance inside ordinary production AI systems.